nju3555 nju3555 NJU8714 -1- ver.2004-05-21 stereo btl outputs switching driver for class d amplifier general description the NJU8714 is a stereo btl outputs switching driver for class d amplifier. it receives pwm/pdm signals from dsp outputs, and drives headphones or speakers by btl outputs. output drivers are composed of series-connected n-channel fets, and output voltage levels can be controlled by variable power supply with keeping all of input signal information. the NJU8714 incorporates btl outputs amplifiers, which eliminate ac coupling capacitors. also, it provides ?sel? terminal which selects ?synchronous? or ?asynchronous?. ?asynchronous? can be reduced the operating current. therefore, it is suitable for portable audio set and others. features 2-channel 1bit audio signal input stereo btl outputs output power : typ.150mw@8 ? beep function standby function output driver control function operating voltage v dd : 1.7v to 2.7v v ddo : 0v to 2.0v v g : 4.5v to 5.25v cmos technology package outline :ssop20-b2 block diagram pin configuration package outline NJU8714vb2 d in2 d in1 beep in m ck s tbyb level shifter v ss pre driver o beep1 o beep2 level shifter level s hif ter level shifter v g v dd haltb level s hif ter v sso out 1 x v ddo1 out 1 v sso out 2 x v ddo2 out 2 control logic control logic level shifter s el pre driver mc k v ss haltb d in1 beep in v dd sel stbyb d in2 v g 1 2 3 4 5 20 19 18 17 16 6 7 8 9 10 o beep1 out 1 v sso out 1 x v ddo1 15 14 13 12 11 o beep2 out 2 v sso out 2 x v ddo2
NJU8714 - 2 - ver.2004-05-21 terminal description no. symbol i/o function 1 mck i master clock input terminal 2 v ss - power gnd: v ss =0v (note.1) 3 haltb i output driver control terminal 4 d in1 i 1bit data input terminal 1 5 beep in i beep signal input terminal 6 o beep1 o beep output terminal 1 7 out 1 o positive output terminal 1 8,13 v sso - output gnd terminal: v ss =0v (note. 1) 9 out 1x o negative output 1 10 v ddo1 - output power supply 1(note. 2) 11 v ddo2 - output power supply 2(note. 2) 12 out 2x o negative output 2 14 out 2 o positive output terminal 2 15 o beep2 o beep output terminal 2 16 v g - pre-driver power supply 17 d in2 i 1bit data input terminal 2 18 stbyb i standby control terminal (l:standby) 19 sel i input signal synchronization with ?mck? (h: synchronous., l: asynchronous.) 20 v dd - power supply: v dd =2.5v (note. 1) pin no.2(v ss ), 8(v sso ) and 13(v sso ) should be connected at the nearest point to the ic. (note. 2) pin no.10(v ddo1 ) and 11(v ddo2 ) should be connected at the nearest point to the ic. input terminal structure mck, haltb, d in1 , d in2 , beep in , stbyb, sel v dd v ss input terminal
nju3555 nju3555 NJU8714 -3- ver.2004-05-21 functional description (1) signal output the out 1/1x and out 2/2x generate respectively l-channel and r-channel output signals, which will be converted to analog signals via external 2nd-order or higher lc filter. a switching regulator with a high response against a voltage fluctuation is the best selection for the v ddo1 and v ddo2 , which are the power supply for output drivers. to obtain better t.h.d. performance, the stabilization of the power is required. (2) master clock (mck) input 1-bit audio signals such as pwm or pdm to the d in1 and d in2 pins. by setting the sel pin to ?h?, master clock (mck) synchronizes the audio signal inputs (d in1 and d in2 ). in case of ?sel? = ?l?, input signals go into the amplifier circuits by own timing. therefore, it requires careful design of pcb patterns from dsp to NJU8714 . the setup time and the hold time should be kept in the ac characteristics because d in1 and d in2 are fetched with the rising edge of mck. mck requires jitter-free or jitter as small as possible because the jitter downs s/n ratio. (3) power supply v dd : power supply for input part. v g : power supply for control logic and pre-driver which drives the transistor gates of output drivers. it requires much higher power supply voltage than v ddo1 and v ddo2 for better t.h.d.. v ddo1 , v ddo2 : power supply for output drivers. (4) output control output circuit is selected by the conditions of stbyb, haltb, sel, d in1 , d in2 and mck. stbyb haltb sel d in1 , d in2 mck out 1 out 2 out 1x out 2x l * * * h l * * * v sso v sso v sso v sso l h * * * hi-z hi-z hi-z hi-z l v sso v sso v ddo1 v ddo2 l h * v ddo1 v ddo2 v sso v sso l v sso v sso v ddo1 v ddo2 h h h h v ddo1 v ddo2 v sso v sso * don?t care beep circuit is operated regardless of stbyb and haltb. (5) input signal synchronization function d in1 and d in2 are synchronized with master clock by setting sel pin to ?h?. by setting sel pin to ?l?, d in1 and d in2 are asynchronous with master clock. (6) output driver control function by setting haltb pin to ?l?, high side output drivers become off and low side output drivers become on, then both of out 1/1x and out 2/2x output v sso level signals. this function works regardless of stbyb pin setting. (7) standby control function by setting stbyb pin to ?l?, the NJU8714 becomes standby condition. during standby condition, by setting haltb to ?l?, out 1/1x and out 2/2x become v sso , and by setting haltb pin to ?h?, out 1/1x and out 2/2x become hi-z. to save the power supply current at standby, mck requires ?l? level.
NJU8714 - 4 - ver.2004-05-21 absolute maximum ratings (ta=25 c) parameter symbol rating unit v dd -0.3 to +2.75 v g v dd to +5.5 supply voltage v ddo -0.3 to +5.5 v input voltage vin -0.3 to v dd +0.3 v operating temperature topr -40 to +85 c storage temperature tstg -40 to +125 c power dissipation p d 450 * mw * : mounted on two-layer board of based on the jedec. note.1) all voltage values are specified as v ss =0v. note.2) if the lsi is used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electrical characteristics conditions will cause malfunction and poor reliability. note.3) the relations of v ddo < v g must be maintained during operations. electrical characteristics (ta=25 c, v dd =2.5v, v g =5.0v, v ddo1 = v ddo2 =1.7v, v ss =v sso =0v, stbyb=haltb=sel=2.5v, load impedance=32 ? , f s =44.1khz, unless otherwise noted) parameter symbol conditions min typ max unit v dd supply voltage v dd - 1.7 2.5 2.7 v ddo1 , 2 input voltage v ddo - 0 - 2.0 v g supply voltage v g - 4.5 5.0 5.25 v output driver high side resistance r hph out 1 , out 1x , out 2 , out 2x = v ddo1 , 2 ? 0.1v v g =5.0v - 1.2 2 ? output driver low side resistance r hpl out 1 , out 1x , out 2 , out 2x = 0.1v v g = 5.0v - 1.2 2 ? beep high side resistance r beeph o beep1 , o beep2 = v dd ? 0.1v - 9.0 15 ? power supply current at standby i st stopping mck, d in1 , d in2 , beep in stbyb= 0v - - 1.0 ua i dd - 0.05 0.1 i ddo - 0.25 0.5 power supply current at operating (mute signal input) i g no-load operating, mck= 256f s , d in1 , d in2 = 32f s , v ddo1 = v ddo2 = 0.18v 1.0 2.0 ma v ih 0.7v dd - v dd v input voltage v il 0 - 0.3 v dd v input leakage current i lk mck, d in1 , d in2 , beep in , haltb, stbyb, sel - - 1.0 ua note 1) high side resistance and low side resistance depend on v g and v ddo . therefore, v g and v ddo should be adjusted on the application system. note 2) output power using 8 ? speaker is 150mw (typ:thd+n=10%) at the following condition. v dd =2.5v, v g =5.0v, v ddo1 = v ddo2 =3.0v
nju3555 nju3555 NJU8714 -5- ver.2004-05-21 timing characteristics ? audio signal input (ta=25 c, v dd =2.5v, v ddo1 =v ddo2 =1.7v, v ss =v sso =0v, stbyb=haltb=sel=2.5v, fs=44.1khz, unless otherwise noted) parameter symbol conditions min typ max unit mck frequency f mcki 8 - 35 mhz mck pulse width (h) t mckh 9 - - ns mck pulse width (l) t mckl 9 - - ns d in1 ,d in2 setup time t ds 5 - - ns d in1 ,d in2 hold time t dh 5 - - ns beep frequency f b 0.1 20 khz ? output control signal input (ta=25 c, v dd =2.5v, v ddo1 =v ddo2 =1.7v, v ss =v sso =0v, stbyb=haltb=sel=2.5v, fs=44.1khz, unless otherwise noted) parameter symbol conditions min typ max unit rise time t up - - 50 ns fall time t dn - - 50 ns t dn t up beep in , haltb stbyb, sel 0.9v dd 0.1v dd t mckh t ds t dh mc k d in1 ,d in2 t mckl 0.7v dd 0.7v dd 0.3v dd 0.3v dd
NJU8714 - 6 - ver.2004-05-21 application circuit -load impedance: 32 ? -load impedance: 8 ? note 3) de-coupling capacitors must be connected between each power supply pin and gnd pin. note 4) the power supply for v ddo requires fast driving response performance such as a switching regulator for t.h.d.. note 5) the above circuit shows only application example and does not guarantee the any electrical characteristics. therefore, please consider and check the circuit carefully to fit your application. v dd v ddo out 1x (9) out 1 (7) stbyb ( 18 ) mck(1) v dd (20) d in1 (4) d in2 (17) haltb(3) v ss (2) NJU8714 v sso (8) 100uf 2.2uf v ddo1 (10) v sso (13) v ddo2 (11) speaker 32 ? 0.22uf 100uh 0.22uf 100uh out 2x (12) out 2 (14) v g (16) v g 10uf 2.2uf 100uf 2.2uf 10uf 2.2u sel ( 19 ) speaker 32 ? 0.22uf 100uh 0.22uf 100uh v dd v ddo out 1x (9) out 1 (7) stbyb ( 18 ) mck(1) v dd (20) d in1 (4) d in2 (17) haltb(3) v ss (2) NJU8714 v sso (8) 100uf 2.2uf v ddo1 (10) v sso (13) v ddo2 (11) speaker 8 ? 1.0uf 22uh 1.0uf 22uh out 2x (12) out 2 (14) v g (16) v g 10uf 2.2uf 100uf 2.2uf 10uf 2.2u sel ( 19 ) speaker 8 ? 1.0uf 22uh 1.0uf 22uh
nju3555 nju3555 NJU8714 -7- ver.2004-05-21 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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